PUBLICATIONS
Conference Material
Below are all presentations, papers, posters, and videos from RISC-V in Space Workshop 2025.
The recorded talks from the second day will be published within soon.
Speakers
April 2nd, 2025
Welcome
CHAIRMAN’S WELCOME
Sandi Habinc – Frontgrade Gaisler
TECHNICAL CHAIR’S WELCOME
Roland Weigand – European Space Agency
LORD MAYOR’S WELCOME
Margareta Broang – City of Gothenburg
WELCOME TO SWEDEN
Dr. Ella Carlsson – Swedish National Space Agency
session – RISC-V IP CORES
KEYNOTE – Benefits the RISC-V Architecture can Bring to the Space Ecosystem
Andrea Gallo – RISC-V International
RVMC/NOEL3 – A new RISC-V Microcontroller CPU Core
Alfonso Carballo Boullosa – Frontgrade Gaisler
RISC-V Core for Space Microcontroller Applications in Airbus Crisa
Juan Antonio Ortega Ruiz – Airbus Crisa
PLATINUM SPONSOR – Challenges of New Space Platforms
Lorne Graves – Frontgrade Technologies
session – ai oriented developments
KEYNOTE – Space Application – Leveraging FPGAs and RISC-V
Göran Bilski – AMD
The ISOLDE Space Demonstrator: A Platform for AI Applications on Satellites
Dr. Antonio Sciarappa – Leonardo
The METASAT Space Platform: High Performance On-Board Processing for Institutional Missions Using Multicores, GPU and AI Accelerator
Dr. Leonidas Kosmidis – Barcelona Supercomputing Center
Astral: a Mixed-Criticality RISC-V SoC Architecture for Satellite Onboard AI
Yvan Tortorella – Fondazione Chips-IT Italy
AI/ML for Space Applications on RISC-V: A Fully European Technology Stack Analysis
Dr. Pablo Ghiglin, Jean-Didier Noir – Klepsydra Technologies
GOLD SPONSOR – The Future of Neuromorphic, event-based Processing in Space: What will the next generation Akida IP make possible
Alf Kuchenbuch – BrainChip Inc.
session – radiation and flight results
KEYNOTE – Open RISC-V Hardware in Space – One Small Step for Space, One Giant Leap for PULP
Dr. Frank Kagan Gurkaynak – ETH Zürich
Efficacy of Radiation Hardening by Design Techniques on an ASIC 32-bit RISC-V Microcontroller
Christopher Elash – University of Saskatchewan
SEE Characterization of NOEL-V on 28nm FD-SOI Platform for Space
Dr. Lucas Antunes Tambara – Frontgrade Gaisler
HARV – Hardened RISC-V System-on-Chip
Douglas Almeida dos Santos – University of Montpellier
SILVER SPONSOR – Develop your next RISC-V-based spacecraft with a digital twin in Renode
Piotr Zierhoffer – Antmicro
SILVER SPONSOR – Ensuring Ultra-reliable RISC-V Designs for Space
Adnan Hamid – Breker Verification Systems
session – Chip Implementations & Architectures
KEYNOTE – We have lift-off! The Past, Present and Future of RISC-V in Space
Ted Speers – Microchip Technology Inc.
DUROC Demonstrator in Radiation Hardened 7nm FinFET Technology
Dr. Alp Kilic – NanoXplore
High-Performance 64-bit HPSC Microprocessor (MPU) New Era of Autonomous Space Computing
Nicolas Ganry – Microchip France
GR765 – Octa-Core Rad-Hard Microprocessor
Magnus Hjorth – Frontgrade Gaisler
Akida: a Hardware Accelerator for AI Tasks, for Integration with RISC-V Systems
Dr. Douglas McLelland – BrainChip
SILVER SPONSOR – World’s First 50 TOPS RISC-V Modular and Upgradable AI Laptop for Advanced Space Systems Development
Yuning Liang – DeepComputing
April 3rd, 2025
session – Extensions, Fault Tolerance and Interconnects
KEYNOTE – RISC-V and EuroHPC – Powering Europe’s Future in High-Performance Computing
Dr. Alexandra Kourfali – EuroHPC Joint Undertaking
Fault-Tolerant RISC-V Softcore: SRAM-Based FPGA Implementation and Reliability Testing
Dr. Fernanda Kastensmidt – UFRGS University
Enhancing RISC-V Ecosystem for SEU-Resilient Inference on FPGA-Based Implementations
Giorgio Cora – Politecnico di Torino
Enhancing Cache Coherent Interconnects to Support Space Systems
Mehrzad Nejat – Chalmers University of Technology
Tightly-coupled VS Loosely-coupled Accelerators for Data Compression in Space Applications: a NOEL-V Study Case
Dr. Enrico Manfredi – Politecnico di Torino
GOLD SPONSOR – System Bus Access: Gaining Runtime Insights through the Debugger
Johannes Lask – SEGGER
session – Security, Safety and Reliability
KEYNOTE – Take Back Control with RISC-V
Jimmy Le Rhun – Thales CortAIx Labs
Analysing Transient Execution Attacks Feasibility on the NOEL-V Platform
Gianluca Furano – European Space Agency
ENGAGE-V: A RERI-Compliant RISC-V Module for RAS in Space Applications
Prof. Daniele Rossi – University of Pisa
Flexible and secure payload integration; CDPU a RISC-V ’New Space’ approach
Dr. Gerard Rauwerda – Technolution B.V.
Enhancing Maintainability and Reliability in Space Applications: A RISC-V Based System Controller for High-Performance Data Processing Units for Small Satellites Using LiteX
Daniel Garbe – Fraunhofer EMI
GOLD SPONSOR – Full System Modeling and Simulation for RISC-V Platform Co-Design
John Leidel – Tactical Computing Labs
session – Software, Verification and Tools
KEYNOTE – All-in-one CPU, Vector and Tensor RISC-V Computing from Semidynamics
Dr. Roger Espasa – Semidynamics
Test-in-the-loop: Designing RISC-V Soft-Cores through Methodic Validation
Tijmen Smit – University of Twente
RISC-V Unified Database
Afonso Oliveira – Universidade do Minho / Synopsys, Inc.
Embracing Both Emulation and Simulation: Shift-Left and Continuous Functional Testing for Space Software
Dr. James Hui – Windriver
KEYNOTE – Ultra-Deep Submicron Technologies for European Space Sovereignty: Advancing Next-Generation Processors and System Integration
Boris Glass – European Space Agency
SILVER SPONSOR – How we accidental ended up in Space – OpenHW Foundation
Flo Wohlrab – OpenHW Group
Posters
Ensuring Security and Reliability in Space Microprocessors with Hardware-Based Techniques
Prof. Alessandro Palumbo – CentraleSupelec, IRISA, Inria
A Hardware Accelerator for Secure Communications through Post Quantum Cryptography
Ambily Suresh- Silicon Austria Labs
Fault-Tolerant Soft RISC-V Linux SoCs on SRAM-based FPGAs in Space
Andrew Wilson – Brigham Young University
Securing Modern Satellite Architectures and Ensuring Software Integrity
Astrid Courtay – Irdeto
RISC-V * N
Barry Kavanagh – O.C.E. Technology Ltd
SweRISC PISCES – A Swedish RISC-V Processor in Silicon Carbide for Extreme Space Environments
Prof. Carl-Mikael Zetterling – KTH Royal Institute of Technology
Porting an ECSS Qualified Flight Boot Loader Software to RISC-V Architecture
Daniel Hellström – Frontgrade Gaisler
Onboard Computer Case-Study on RISC-V Core
Dr. Fernanda Kastensmidt – UFRGS University
Heterogeneous Multicore Debugging of Space-Dedicated RISC-V Chips Made Easy
Kristoffer Martinsson – Nohau/Lauterbach
GRAIN – Radiation-Tolerant Edge AI
Kenneth Östberg – Frontgrade Gaisler
FPGA Accelerated Post-Synthesis Fault Injection for RISC-V Cores
Eike Trumann – TU Braunschweig
RADLER: A Permissive Open Source Hardware Platform for Increased Autonomy
Dr. Leonidas Kosmidis – Barcelona Supercomputing Center
Accelerating CCSDS121 in RISC-V with Custom Instructions
Dr. Martin Danek – daiteq s.r.o.
Safety Qualification of Open Source Software
Dr. Matthias Göbel – embedded brains GmbH &Co KG
EMSA5: A RISC-V Processor System for Enhanced Functional Safety in Embedded Applications
Dr. Michael Faulwaßer – Fraunhofer IPMS
The RERI-Lite Error Logging Framework
Michiel Koenderink – University of Twente
An Overview of Available and Upcoming RISC-V Security Mechanisms, and their Potential use in Satellite as a Service Scenarios
Nick Kossifidis – Institute of Computer Science, Foundation for Research and Technology – Hellas (FORTH)
High-Performance AI/ML Inference for Space Applications on RISC-V: A Comparative Performance Analysis
Dr. Pablo Ghiglino – Klepsydra Technologies
Virtual Prototyping for Space Applications – How to get custom SoCs done Fast and Correct
Pascal Pieper – DLR RY-AVS
Secure Boot and Root-of-Trust for Space-Grade RISC-V Systems
Jan Andersson – Frontgrade Gaisler for Xiphera Ltd
Highly Parallel Rad-Hard RISC-V-based Manycore Accelerators
Prof. Ran Ginosar – Ramon Space
Fast Single Event Upset Detection Technique for Processors
Stefan De Raedemaeker – KU Leuven
Master Thesis Posters
MemoryBoost: RISC-V Temporal Isolation Through Dynamic Hypervisor-level Bandwidth Reservation
Afonso Oliveira – Universidade do Minho
Anomaly Detection for Dependable RISC-V-based Systems in Safety-Critical Applications
Niccolò Frascarelli – Università di Pisa
Development of Radiation Tolerant Data Acquisition System for a Langmuir Probe Instrument
Romina Gaudio Couselo – Kungliga Tekniska Högskolan
Instrument Software Development for Langmuir Probe Onboard ROMEO Satellite
Sergiu Bogdan Popescu – Kungliga Tekniska Högskolan
Coherent On-chip Architecture Evaluation for RISC-V Multi-processor
Veronica Kimelman & Alex Helmersson – Chalmers Tekniska Högskola
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